IBM, Siemens Partner to Advance 3D Nanostack Transistors Beyond 7 Angstroms

IBM has joined forces with Siemens on semiconductor research aimed at moving its nanostack transistor architecture closer to scalable manufacturing, combining IBM’s device development expertise with Siemens’ capabilities in electronic design automation, process simulation and lithography optimisation.

The companies will work on the design, modelling and manufacturing techniques required for future generations of nanostack technology, including architectures beyond IBM’s current 7-angstrom, or 0.7 nm, node.

A key part of the collaboration will involve creating advanced virtual models of the nanostack architecture. These models are intended to help engineers predict device behaviour, optimise designs and identify potential manufacturing problems before physical chips are produced.

Siemens will contribute expertise across EDA software, process simulation, lithography optimisation and advanced manufacturing tools, while IBM will provide its semiconductor device and process technology research.

Nanostack Takes Transistor Scaling into the Third Dimension

IBM introduced its nanostack architecture earlier in 2026 as part of its sub-1 nm semiconductor research.

Instead of relying primarily on shrinking transistor dimensions across a two-dimensional surface, nanostack places nanosheet-based transistors vertically above one another. IBM describes the technology as the industry’s first known three-dimensional nanosheet architecture, using vertically stacked and staggered devices to increase transistor density.

At the 7-angstrom generation, IBM says the technology can accommodate nearly 100 billion transistors on a chip measuring about 150 mm², roughly the size of a fingernail and nearly twice the transistor density of its earlier 2 nm technology.

The architecture can also use different semiconductor material combinations within separate transistor layers. That could allow engineers to optimise individual layers for performance or power efficiency rather than applying the same material approach across the entire device.

The ability to build upwards is becoming increasingly important as conventional lateral transistor scaling becomes harder at angstrom dimensions.

IBM and Siemens Focus on Manufacturing Challenges

Demonstrating a new transistor architecture is only one stage in bringing it into commercial chip production.

IBM and Siemens will therefore concentrate on the simulation, design and lithography challenges that could determine whether nanostack devices can eventually be manufactured reliably and at scale.

Huiming Bu, Vice President of Silicon Technology R&D at IBM, said nanostack is intended to move logic scaling from two dimensions into three dimensions, providing another route for increasing semiconductor density as demand from AI and other compute-intensive applications continues to rise.

Ankur Gupta, Executive Vice President of the EDA IC Portfolio at Siemens, said semiconductor scaling into the angstrom era increasingly requires device physics, EDA software and manufacturing technologies to be developed together rather than independently.

That co-optimisation is particularly important for vertically stacked devices because additional layers introduce challenges involving thermal behaviour, device interactions, interconnects, lithography and process variability.

Virtual modelling could allow many of those issues to be studied earlier in the development process, reducing the number of physical fabrication cycles required before a design is ready for more advanced manufacturing trials.

IBM Prepares Nanostack Design Ecosystem

IBM is also beginning to build a wider design ecosystem around the architecture.

On 13 October 2026, the company said it plans to make an early research and development process design kit, or PDK, for its 7-angstrom nanostack technology available in the first quarter of 2027.

The PDK is intended to allow semiconductor designers, EDA companies, equipment suppliers and researchers to begin studying how products and manufacturing processes could be adapted for the new architecture.

IBM has said early access could support research into areas including parasitic extraction, thermal coupling and interactions between neighbouring devices, while giving EDA suppliers time to adapt design tools before the technology reaches a more mature stage.

The Siemens partnership fits into that broader effort. Rather than treating transistor architecture, design tools and manufacturing as separate development stages, the companies are seeking to address those requirements simultaneously.

For the semiconductor industry, nanostack represents another attempt to extend logic scaling as conventional transistor shrinkage becomes more difficult. Whether the architecture reaches high-volume production will depend not only on IBM’s ability to demonstrate increasingly dense devices, but also on whether EDA tools, lithography processes and manufacturing techniques can evolve quickly enough to make vertically stacked transistors practical at commercial scale.